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 Preliminary Datasheet
RJE0609JPD
Silicon P Channel MOS FET Series Power Switching
Description
This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of high junction temperature like applying over power consumption, over current etc.. REJ03G1908-0100 Rev.1.00 Apr 01, 2010
Features
Logic level operation (-6 V Gate drive). Built-in the over temperature shut-down circuit. High endurance capability against to the short circuit. Latch type shut down operation (need 0 voltage recovery). Built-in the current limitation circuit. Low on-resistance 100 m Max (VGS = -10 V)
Outline
RENESAS Package code: PRSS0004ZD-C (Package name: DPAK (S) )
D
4 1. Gate 2. Drain 3. Source 4. Drain
G
Gate Resistor Temperature Sensing Circuit Latch Circuit Gate Shut-down Circuit
1
Current Limitation Circuit
2
3
S
Absolute Maximum Ratings
(Ta = 25C)
Item Symbol Drain to source voltage VDSS Gate to source voltage VGSS Gate to source voltage VGSS Drain current ID Note3 Body-drain diode reverse drain current IDR Avalanche current IAP Note 2 Avalanche energy EAR Note 2 Channel dissipation Pch Note 1 Channel temperature Tch Storage temperature Tstg Notes: 1. Value at Tc = 25C 2. Tch = 25C, Rg 50 3. It provides by the current limitation lower bound value. Ratings -60 -16 2.5 -4 -4 -4 68 30 150 -55 to +150 Unit V V V A A A mJ W C C
REJ03G1908-0100 Rev.1.00 Apr 01, 2010
Page 1 of 6
RJE0609JPD
Preliminary
Typical Operation Characteristics
(Ta = 25C)
Item Input voltage Input current (Gate non shut down) Input current (Gate shut down) Shut down temperature Gate operation voltage Drain current (Current limitation value) Notes; 4. Pulse test Symbol VIH VIL IIH1 IIH2 IIL IIH(sd)1 IIH(sd)2 Tsd Vop ID limt Min -3.5 -- -- -- -- -- -- -- -3.5 -4 Typ -- -- -- -- -- -0.8 -0.35 175 -- -- Max -- -1.2 -100 -50 -1 -- -- -- -12 -- Unit V V A A A mA mA C V A Test Conditions
Vi = -8 V, VDS = 0 Vi = -3.5 V, VDS = 0 Vi = -1.2 V, VDS = 0 Vi = -8 V, VDS = 0 Vi = -3.5 V, VDS = 0 Channel temperature (dv/dt VGS 500 V/ms) VGS = -12 V, VDS = -10 V Note 4
Electrical Characteristics
(Ta = 25C)
Item Drain current Symbol ID1 ID2 ID3 V(BR)DSS V(BR)GSS V(BR)GSS IGSS1 IGSS2 IGSS3 IGSS4 IGS(OP)1 IGS(OP)2 IDSS VGS(off) |yfs| RDS(on) RDS(on) Coss td(on) tr td(off) tf VDF trr tos1 Min -- -- -4 -60 -16 2.5 -- -- -- -- -- -- -- -2.2 2 -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -0.8 -0.35 -- -- 4.3 102 79 290 2.97 2.58 1.55 1.05 0.84 81 5.7 Max -4 -10 -- -- -- -- -100 -50 -1 100 -- -- -10 -3.4 -- 170 100 -- -- -- -- -- -- -- -- Unit A mA A V V V A A A A mA mA A V S m m pF s s s s V ns ms Test Conditions VGS = -3.5 V, VDS = -10 V VGS = -1.2 V, VDS = -10 V VGS = -12 V, VDS = -10 V Note 5 ID = -10 mA, VGS = 0 IG = -800 A, VDS = 0 IG = 100 A, VDS = 0 VGS = -8 V, VDS = 0 VGS = -3.5 V, VDS = 0 VGS = -1.2 V, VDS = 0 VGS = 2.4 V, VDS = 0 VGS = -8 V, VDS = 0 VGS = -3.5 V, VDS = 0 VDS = -60 V, VGS = 0 VDS = -10 V, ID = -1 mA ID = -2 A, VDS = -10 V Note 5 ID = -2 A, VGS = -6 V Note 5 ID = -2 A, VGS = -10 V Note 5 VDS = -10 V, VGS = 0, f = 1MHz VGS = -10 V, ID= -2 A, RL = 15
Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current
Input current (shut down) Zero gate voltage drain current Gate to source cutoff voltage Forward transfer admittance Static drain to source on state resistance Output capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Body-drain diode reverse recovery time Over load shut down Note 6 operation time
IF = -4 A, VGS = 0 IF = -4 A, VGS = 0 diF/dt = 50 A/s VGS = -6 V, VDD = -16 V
Notes: 5. Pulse test 6. Including the junction temperature rise of the over loaded condition.
REJ03G1908-0100 Rev.1.00 Apr 01, 2010
Page 2 of 6
RJE0609JPD
Preliminary
Main Characteristics
Power vs. Temperature Derating
80 -100
Ta = 25C
Maximum Safe Operation Area
Channel Dissipation Pch (W)
60
Drain Current ID (A)
Thermal shut down operation area
-10
1 s m
40
-1
PW = 10 ms DC Operation (Tc = 25C) Operation in this area is limited RDS(on)
20
0 0 50 100 150 200
-0.1 -0.01
-0.1
-1
-10
-100
Case Temperature Tc (C)
Drain to Source Voltage VDS (V)
Typical Output Characteristics
-10 V -4 -7 V -6 V -5.5 V -5 V -4.5 V -4 V -4 Pulse Test
Typical Transfer Characteristics
VDS = -10 V Pulse Test
Drain Current ID (A)
Drain Current ID (A)
-3
-3
-2
-2
150C
-1
-1
25C
0
VGS = 0 V 0 -2 -4 -6 -8 -10
Tc = -40C 0 0 -2 -4 -6 -8 -10
Drain to Source Voltage VDS (V) Drain Source Saturation Voltage vs. Gate to Source Voltage
Drain to Source Saturation Voltage VDS(on) (mV)
-2000 -1600 -1200 -800 -400 -0.5 A 0 0 -2 -4 -6 -8 -10 -1 A ID = -2 A Pulse Test
Gate to Source Voltage VGS (V) Static Drain to Source On State Resistance vs. Drain Current
1000 Pulse Test
Static Drain to Source On State Resistance RDS(on) (m)
100
-6 V VGS = -10 V
10
1 -0.1
-1
-10
Gate to Source Voltage VGS (V)
Drain Current ID (A)
REJ03G1908-0100 Rev.1.00 Apr 01, 2010
Page 3 of 6
RJE0609JPD
Static Drain to Source On State Resistance vs. Temperature
Forward Transfer Admittance |yfs| (S)
200 Pulse Test ID = -0.5 A -1 A -2 A -6 V ID = -0.5 A -1 A -2 A 75 100 125 150 100
Preliminary
Forward Transfer Admittance vs. Drain Current
VDS = -10 V Pulse Test
Static Drain to Source On State Resistance RDS(on) (m)
150
10
Tc = -40C
25C 1 150C
100
VGS = -10 V 50 -50 -25 0 25 50
0.1 -0.1
-1
-10
Case Temperature Tc (C)
Drain Current ID (A)
Body-Drain Diode Reverse Recovery Time
Reverse Recovery Time trr (ns)
1000 di / dt = 100 A / s VGS = 0, Ta = 25C 10
Switching Characteristics
Switching Time t (s)
td(on) tr td(off) 1 tf
100
10 -0.1
-0.3
-1
0.1 -0.1
VGS = -10 V, VDD = -30 V PW = 300 s, duty 1 % -1 -10
Reverse Drain Current IDR (A) Reverse Drain Current vs. Source to Drain Voltage
-5
Drain Current ID (A) Typical Capacitance vs. Drain to Source Voltage 1000
Reverse Drain Current IDR (A)
Capacitance C (pF)
-4 -3 -5 V -2 -1 -10 V Pulse Test 0 -0.4 -0.8 -1.2 -1.6 -2.0 VGS = 0 V, 5 V, 10 V
Coss
100
VGS = 0 f = 1 MHz
10 0
-10 -20 -30 -40 -50 -60
Source to Drain Voltage VSD (V)
Drain to Source Voltage VDS (V)
REJ03G1908-0100 Rev.1.00 Apr 01, 2010
Page 4 of 6
RJE0609JPD
Gate to Source Voltage vs. Shutdown Time of Load-Short Test
Gate to Source Voltage VGS (V)
-16 -14 -12 -10 -8 -6 -4 -2 0 1 10 100 VDD = -16 V
Preliminary
Shutdown Case Temperature vs. Gate to Source Voltage
Shutdown Case Temperature Tc (C)
200
180
160
140 ID = -1 A dv / dt VGS 500 V/ ms 0 -2 -4 -6 -8 -10
120 100
Shutdown Time of Load-Short Test Pw (ms)
Normalized Transient Thermal Impedance s (t)
Gate to Source Voltage VGS (V)
Normalized Transient Thermal Impedance vs. Pulse Width
10
Tc = 25C
1
D=1 0.5 0.2
0.1
0.1 0.05 0.02
0 .01
h 1s ot pu lse
ch - c(t) = s (t) * ch - c ch - c = 4.17C/W, Tc = 25C
PDM PW T
D=
PW T
0.01 10
100
1m
10 m
100 m
1
10
Pulse Width PW (S) Switching Time Test Circuit
Vin Monitor D.U.T. RL VDD = -30 V Vout td(on) Vout Monitor Vin 10% 90% 90% 90%
Waveform
Vin -10 V
50
10% tr td(off)
10% tf
REJ03G1908-0100 Rev.1.00 Apr 01, 2010
Page 5 of 6
RJE0609JPD
Preliminary
Package Dimensions
Package Name DPAK(S) JEITA Package Code SC-63 RENESAS Code PRSS0004ZD-C Previous Code DPAK(S) / DPAK(S)V MASS[Typ.] 0.28g
Unit: mm
1.5 0.5
6.5 0.3 5.6 0.5
2.3 0.2 0.55 0.1
(5.1)
5.5 0.5
1.2 Max
0 - 0.25
(1.2)
2.5 0.5
1.0 Max. 2.29 0.5
0.8 0.1 2.29 0.5
0.55 0.1
Ordering Information
Part No. RJE0609JPD-00-J3 Quantity 3000 pcs Shipping Container Taping (Sinistrorse)
REJ03G1908-0100 Rev.1.00 Apr 01, 2010
(5.1)
Page 6 of 6
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 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